ISO/IEC 15776:2001 VME64bus —仕様 | ページ 4

1.1 範囲と目的

VMEbus 仕様は、密接に結合されたハードウェア構成でマイクロプロセッサ、データ ストレージ、および周辺制御デバイスを相互接続するために使用されるインターフェイス システムを定義します。このシステムは、次の目的で考案されました。

• a) VMEbus に接続された他のデバイスの内部活動を妨害することなく、VMEbus 上のデバイス間の通信を可能にする。
• b) VMEbus に接続された他のデバイスと確実かつ明確に通信するデバイスを設計するために必要な電気的および機械的システムの特性を指定する。
• c) VMEbus とそれに接続されたデバイスとの間の相互作用を正確に定義するプロトコルを指定する。
• d)システムプロトコルを説明する用語と定義を提供する。
• e)設計者がシステムの互換性に影響を与えずにコストおよび/または性能を最適化できるように、幅広い設計自由度を許可する。
• f)パフォーマンスが、システム インターフェイスの制限ではなく、主にデバイスの制限であるシステムを提供すること。

1.3.1.1 VMEbus の機械構造

1.5.1 信号線の状態

VMEbus 仕様では、バス ラインのレベルと遷移の観点からプロトコルを説明しています。

信号線は、常に 2 つのレベルのいずれか、またはこれらのレベル間の遷移にあると見なされます。 「高」という用語が使用される場合は常に、高い TTL 電圧レベルを指します。 「低」という用語は、低い TTL 電圧レベルを指します。電圧がこれらのレベル間を移動しているとき、信号線は「遷移中」です。 (VMEbus で使用される電圧しきい値については、6 節を参照してください。)

信号線に現れる可能性のある 2 つの遷移があり、これらは「エッジ」と呼ばれます。立ち上がりエッジは、信号レベルがロー レベルからハイ レベルに遷移する時間です。立ち下がりエッジは、信号レベルがハイ レベルからロー レベルに遷移する時間です。

一部のバス仕様では、これらのエッジの最大または最小の立ち上がり時間と立ち下がり時間が規定されています。これを行う際の問題は、ボード設計者がこれらの時間をほとんど制御できないことです。バックプレーンの負荷が大きい場合、立ち上がり時間と立ち下がり時間は長くなります。負荷が軽い場合、これらの時間は短くなる可能性があります。設計者は、負荷の最大値と最小値がわかっている場合でも、ラボで時間をかけて実験し、必要な立ち上がり時間と立ち下がり時間を提供するドライバーを見つける必要があります。

実際、立ち上がり時間と立ち下がり時間は、バックプレーンの信号ライン インピーダンス、その終端、ドライバーのソース インピーダンス、および信号ラインの容量負荷を含む一連の複雑な相互作用の結果です。これらすべての要因をトレードオフするために、ボード設計者は伝送線路の理論と、ほとんどのメーカーのデータシートには通常見られないドライバーとレシーバーの特定のパラメーターを研究する必要があります。

このすべてを認識して、VME​​bus 規格は立ち上がり時間と立ち下がり時間を指定していません。代わりに、ドライバーとレシーバーの電気的特性を指定し、バックプレーンの設計を指定します。また、最悪の場合のバス負荷がこれらのドライバーの伝播遅延にどのように影響するかを設計者に伝え、ボードを構築する前に VMEbus タイミングが確実に満たされるようにします。 VMEbus 設計者がこれらの伝搬遅延ガイドラインに従う場合、そのボードは最悪の条件下でも他の VMEbus 互換ボードで確実に動作します。

システム性能は、オープンコレクタ制御信号の 1 つの立ち上がり時間に影響されます。システムのパフォーマンスを向上させるために、取り消し信号の概念が導入されました。取り消し信号はオープン コレクタ タイプの出力で、最初にハイに駆動され、その後短時間でオープン コレクタ モードに戻ります。

1.6.1 連動バス信号

インターロックバス信号は、特定のモジュールから別の特定のモジュールに送信されます。信号は受信モジュールによって確認されます。信号が確認されるまで、2 つのモジュール間に連動関係が存在します。

たとえば、インタラプタは、後で割り込み確認信号で応答される割り込み要求を送信できます (VMEbus 仕様では時間制限は規定されていません)インタラプタは、割り込みハンドラが応答するまで割り込み要求を削除しません。

インターロックされたバス信号は、外部刺激と相互作用するのではなく、VMEbus システムの内部機能を調整します。各連動信号には、VMEbus システム内にソース モジュールと宛先モジュールがあります。

アドレスストローブとデータストローブは特に重要な連動信号です。これらは、データ転送アクノレッジおよびバス エラー信号と連動し、データ転送層のモジュール間のすべての情報フローの基礎となるアドレスとデータの転送を調整します。

1 General

1.2 Normative references

The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.

1.3 VMEbus interface system elements

1.3.1 Basic definitions

The VMEbus structure can be described from two points of view: its mechanical structure and its functional structure. The mechanical specification describes the physical dimensions of subracks, backplanes, front panels, plug-in boards, etc. The VMEbus functional specification describes how the bus works, what functional modules are involved in each transaction, and the rules which govern their behavior. The following informal definitions describe some basic terms used for both the mechanical and the functional structure of the VMEbus.

1.3.1.2 VMEbus functional structure

Figure 1 shows a simplified block diagram of the functional structure, including the VMEbus signal lines, backplane interface logic, and functional modules.

1.3.1.3 Types of cycles on the VMEbus

1.3.2 Basic VMEbus structure

The VMEbus interface system consists of backplane interface logic, four groups of signal lines called buses, and a collection of functional modules which can be configured as required. The functional modules communicate with each other using the backplane signal lines.

The functional modules defined in this document are used as vehicles for discussion of the bus protocol and need not be considered a constraint to logic design. For example, the designer might choose to design logic which interacts with the VMEbus in the manner described, but uses different onboard signals, or monitors other VMEbus signals. VMEbus boards might be designed to include any combination of the functional modules defined by this standard.

The VMEbus functional structure can be divided into four categories. Each consists of a bus and its associated functional modules which work together to perform specific duties. Figure 2 shows the VMEbus functional modules and buses. Each category is briefly summarized below.

1.4 VMEbus specification diagrams

As aids to defining or describing VMEbus operation, several types of diagrams are used, including:

• a) Timing diagrams that show the timing relationships between signal transitions. The times involved will have minimum and/or maximum limits associated with them. Some of the times specified on these diagrams specify the behavior of the backplane interface logic, while other times specify the interlocked behavior of the functional modules.
• b) Sequence diagrams that are similar to timing diagrams but show only the interlocked timing relationships of the functional modules. These diagrams are intended to show a sequence of events, rather than to specify the times involved. For example, a sequence diagram might indicate that module A cannot generate signal transition B until it detects module C's generation of signal transition D.
• c) Flow diagrams that show a stream of events as they would occur during a VMEbus operation. The events are stated in words and result from interaction of two or more functional modules. The flow diagram describes VMEbus operations in a sequential manner and, at the same time, shows interaction of the functional modules.

1.5 Specification terminology

To avoid confusion, and to make very clear what the requirements for compliance are, many of the paragraphs in this document are labelled with keywords that indicate the type of information they contain. The keywords are listed below

RULE

RECOMMENDATION

SUGGESTION

PERMISSION

OBSERVATION

Any text not labelled with one of these keywords describes the VMEbus structure or operation. It is written in either a descriptive or a narrative style. These keywords are used as follows:

RULE chapter.number

Rules form the basic framework of the VMEbus specification. They are sometimes expressed in text form and sometimes in the form of Figures, tables, or drawings. All VMEbus rules MUST be followed to ensure compatibility between VMEbus designs. Rules are characterized by an imperative style. The upper-case words MUST and MUST NOT are reserved exclusively for stating rules in this document and are not used for any other purpose.

RECOMMENDATION chapter.number

Wherever a recommendation appears, designers would be wise to take the advice given. Doing otherwise might result in some awkward problems or poor performance. While the VMEbus has been designed to support high performance systems, it is possible to design a VMEbus system that complies with all the rules, but has abysmal performance. In many cases, a designer needs a certain level of experience with the VMEbus in order to design boards that deliver top performance. Recommendations found in this document are based on this kind of experience and are provided to designers to speed their traversal of the learning curve.

SUGGESTION chapter.number

In the VMEbus specification, a suggestion contains advice which is helpful but not vital. The reader is encouraged to consider the advice before discarding it. Some design decisions that need to be made in designing VMEbus boards are difficult until experience has been gained with the VMEbus. Suggestions are included to help a designer who has not yet gained this experience. Some suggestions have to do with designing boards that can be easily reconfigured for compatibility with other boards, or with designing the board to make the job of system debugging easier.

PERMISSION chapter.number

In some cases a VMEbus rule does not specifically prohibit a certain design approach, but the reader might be left wondering whether that approach might violate the spirit of the rule, or whether it might lead to some subtle problem. Permissions reassure the reader that a certain approach is acceptable and will cause no problems. The upper-case word MAY is reserved exclusively for stating permissions in this document and is not used for any other purpose.

OBSERVATION chapter.number

Observations do not offer any specific advice. They usually follow naturally from what has just been discussed. They spell out the implications of certain VMEbus rules and bring attention to things that might otherwise be overlooked. They also give the rationale behind certain rules, so that the reader understands why the rule must be followed.

1.5.2 Use of the asterisk (*)

To help define usage, signal mnemonics have an asterisk suffix where required.

• a) An asterisk (*) following the signal name of signals which are level significant denotes that the signal is true or valid when the signal is low.
• b) An asterisk (*) following the signal name of signals which are edge significant denotes that the actions initiated by that signal occur on a high to low transition.

OBSERVATION 1.1

The asterisk is inappropriate for the asynchronously running clock line SYSCLK. There is no fixed phase relationship between this clock line and other VMEbus timing.

1.5.3 Keyword numbering

This standard is based on previous standards. To preserve keyword numbering, new keywords (rules, recommendation, suggestions, permissions, observations) have been numbered starting from the last available number. Hence, keywords as presented throughout this standard are not necessary in sequential order. See keyword cross-reference index to determine where a specific keyword is referenced.

1.6 Protocol specification

There are two layers of VMEbus protocol. The lowest VMEbus layer, called the backplane access layer, is composed of the backplane interface logic, the Utility Bus modules, and the Arbitration Bus modules. The VMEbus data transfer layer, is composed of the Data Transfer Bus and Priority Interrupt Bus modules. Figure 2 shows this layering.

OBSERVATION 1.2

The signal lines used by the data transfer layer modules form a special class because they are driven by different modules at different times. They are driven with line drivers that can be turned on and off at each board based upon signals generated in the backplane access layer. It is very important that their turn-on and turn-off times be carefully controlled to prevent two drivers from attempting to drive the same signal line to different levels. Special timing diagram notation is used in this document to specify their turn-on and turn-off times. It is shown in Figure 3.

There are two basic kinds of protocol used on the VMEbus: closed loop protocols and open loop protocols. Closed loop protocols use interlocked bus signals while open loop protocols use broadcast bus signals.

1.6.2 Broadcast bus signal

A module generates a broadcast signal in response to an event. There is no protocol for acknowledging a broadcast signal. Instead, the broadcast is maintained for a minimum specified time, long enough to assure that all appropriate modules detect the signal. Broadcast signals might be activated at any time, irrespective of any other activity taking place on the bus. They are each sent over a dedicated signal line. Some examples are the system reset and a.c. failure lines. These signal lines are not sent to any specific module, but announce special conditions to all modules.

1.7 System examples and explanations

A protocol specification describes, in detail, the behavior of the various functional modules. It discusses how a module responds to a signal without saying where the signal came from. Because of this, a protocol specification does not give the reader a complete picture of what is going on over the bus. To help the reader, the VMEbus specification provides examples of typical VMEbus operations. Each example shows one possible sequence of events; other sequences are also possible. In providing these examples, there is the danger that readers will assume that the sequence shown in the example is the only legal one. To help readers avoid this trap, all examples are given in a narrative style, using the present tense. This is in contrast to the imperative style used when giving rules for compliance with the VMEbus specification.